SDRAM Under Evaluation With Intel's Next-Gen Chip Set

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Infineon Technologies announced here its initial 512MB DDR2 (second-generation Double-Data-Rate) SDRAM is successfully booting and is under evaluation with Intel's next-generation, dual-processor server chipset code-named 'Lindenhurst'. The DDR components, designed for next-generation servers, PCs, and workstation applications, are fabricated using Infineon's 110 nanometer (nm) CMOS process technology; which results in low power consumption and one of the smallest chip sizes in the industry for this density.

The initial components operate at per pin data rates of 400Mbps and 533Mbps. Components and memory modules operating at higher speeds are already in preparation for systems using DDR2. Infineon's roadmap for DDR2 also includes 256MB and 1GB components in 2004.

The JEDEC-compliant 512MB chips are configured as quad-bank DRAMs; will be available in X4, X8, and X16 organizations; and are offered in fine pitch ball grid array (FBGA) packages. Additional features of the new memory include a pre-fetch size of four bits, differential strobe, and variable data-output impedance adjustment.

Infineon
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